XOR, 4 Inpt
Contents

1.Description

Exclusive or.
If there is a 1 on an uneven number of inputs, a one is output at Output 1.
If there is a 1 on an even number of inputs, a zero is output at Output 1.
Important
Input values which are not equal to zero are entered into the link as 1.

2.Inputs

No.NameInitialisationDescription
1E10
Input value 1.
2E20
Input value 2.
3E30
Input value 3.
4E40
Input value 4.

3.Outputs

No.NameInitialisationSBCDescription
1A10s
The linking result of the inputs is output here. A 1-bit value is output.
2A2 neg0s
The negated linking result of the inputs is output here. A 1-bit value is output.
3A3 (sbc)0sbc
The linking result of the inputs is output here. A 1-bit value is output. Output does not send during a restart.
4A4 neg (sbc)0sbc
The negated linking result of the inputs is output here. A 1-bit value is output. Output does not send during a restart.
s = send, sbc = send by change

4.Value table as an example

All inputsE1E2Z1: Result of E1^E2E3Z2: Result of Z1^E3E4A1 = Z2^E4
0 0 0 00000000
0 0 0 10000011
0 0 1 10001110
0 1 1 10111011
1 1 1 11101110
First, two inputs are linked to one another, then the result with another input value.
The sequence is not important as the following table with all possible combinations of 2 ones and 2 zeros shows:
DistributionE1E2Z1: Result of E1^E2E3Z2: Result of Z1^E3E4A1 = Z2^E4
0 0 1 10001110
0 1 0 10110110
1 0 0 11010110
0 1 1 00111000
1 0 1 01011000
1 1 0 01100000

5.Other

Recalculation during start:Yes
Module is retentive:No
Internal designation:9062
Category:Gate

6.Similar functions

AND, 2 Inpt
AND, 4 Inpt
AND, 8 Inpt
OR, 2 Inpt
OR, 4 Inpt
OR, 8 Inpt
Transfer gate
XOR, 2 Inpt
XOR, 8 Inpt